As is known in the art, RF samplers are commonly used prior to conversion to digital information in an analog to digital converter. Conventionally, the RF Sampler includes several switches that perform the frequency conversion and a baseband filtering network that conditions the output signals.
One frequency conversion application is in phased array antenna systems, such as that is shown in FIG. 1. Here, a phased array system is shown having a plurality of antenna or radiating elements, each one of the elements being coupled to a corresponding one of a plurality of phase shifter sections. Each one of the phase shifter sections includes: an array port coupled to the corresponding one of the antenna elements. Each one of the phase shifter sections directs the signal received by the antenna element coupled to a pair of quadrature channels, each one of the channels having: a down converter section fed by the received RF signal and a local oscillator (LO) signal for converting the received radio frequency (RF) energy received by the antenna element to an intermediate frequency (IF) signal; and as phase shifter section fed by the down conversion section for providing as phase shift to the IF signal selectively in accordance with a phase shift command provided by a beam steering computer (BSC), as shown. The plurality of phase shifters produce, in response to the phase shift commands, a collimated and directed beam. It is understood that the directed beam may be used reciprocally in either a receive mode or, with a circulator or transmit/receive switch, not shown, a transmit mode. Thus, if the all the antenna elements are in-phase the antenna beam is directed along the boresight axis of the array. On the other hand if there is a fixed, non-zero, phase shift across the array, a directed beam is produced having an angle from the boresight axis in accordance with the fixed phase shift.
As is also known in the art, RF Samplers are commonly used to convert RF signals to analog baseband information prior to conversion to digital information in an analog to digital converter. Conventionally, the RF Sampler consists of several switches that perform the frequency conversion and a baseband filtering network that conditions the output signals. By using multiple switches that are active only during a fraction of the input signal cycle, the RF Sampler provides improved noise and loss performance over a conventional mixer.
More particularly, the RF Sampler is formed through the combination of three functions: frequency conversion via the sampling switches, Local Oscillator (LO) generation circuitry to drive the switches, and circuits that provide signal conditioning at the baseband output of the switches. FIG. 2A shows a simplified version of the RF Sampler architecture, where the input RF signal (VRF) is fed into 4 parallel switches (See a paper by Alyosha Molnar and Carline Andrews, “Impedance, Filtering and Noise is N-phase Passive CMOS Mixers,” 2012 IEEE Custom Integrated Circuits Conference (CICC), pp. 1-8, 2012). At the output of the switches, load capacitors form the baseband signal processing circuits. In this case, the baseband circuits are low pass filters. For an RF Sampler architecture with 4 switches, each of the switches are closed with a 25% duty cycle, with the frequency of the switching operation set to the frequency of the RF signal to be down-converted. Each of the 4 switches is closed in quadrature, meaning that only one of the 4 switches is closed at a time, each for ¼ of the cycle time of the RF signal. An equivalent model with is shown in FIG. 2B and the LO driving the waveforms and resulting RF current and virtual voltage Vx is shown in FIG. 2C. One method for generating the necessary LO pulses is to use a bank of dividers driven by a signal at a multiple of the RF signal frequency (FIG. 2C). The four outputs of this RF Sampler then correspond to a differential representation of the in-phase and quadrature component of the down-converted RF signal.
This RF sampling approach differs from conventional mixer architectures in several ways. First, the switch used in the RF Sampler is designed to be as low impedance as possible, ideally providing a perfect short between the RF signal and the baseband filter. Unlike a mixer where the switching function is matched to 50 ohms on both the input and output, the baseband filtering of the RF sampler is effectively translated to RF. The result of this is a passband filter, providing rejection of interfering signals outside of the desired receive band. Through this process, the out-of-band linearity of the RF sampler circuitry is higher than with mixer approaches that often require separate RF filters to be present prior to the frequency converting circuitry. Another key difference is that the impedance to the switch control terminal (the gate, if the switch is a Field Effect Transistor (FET)) is ideally high, and not matched to 50 ohms. In this case, the LO generation circuitry (e.g. a network of dividers) drives the high-impedance switch terminals and ideally alternates each switch between an open and closed state.
RF Samplers are often employed in low-cost commercial applications where frequency conversion is required prior to conversion to the digital domain. The state of the art employs silicon technology, where the switches, the LO generation, and the baseband processing all take place within the same chip technology. Performing all functions on the same chip is the standard approach, as it provides the lowest cost means to achieve the functionality and enables the highest performance by keeping the parasitics between the functional blocks low.
The inventors have recognized that in order to achieve higher RF performance, it would be desirable to use Column III-V (for example GaN) FET switches while using silicon for the LO generation and baseband processing. A low parasitic interface required between the LO generation circuitry and the switches is achieved through either heterogeneous or nearly-heterogeneous packaging approaches, or by resonating out the bondwire parasitic with passive components on the III-V die. An example of a nearly-heterogeneous packaging approach is The Charles Stark Draper Laboratory, Inc., Cambridge, Mass. Integrated-Ultra High Density Packaging (iUHD) technology (U.S. Pat. Nos. 7,726,806 B2; 8,017,451 B2; 8,273,603 B2) or an Redistributed Chip Packaging (RCP) RCP technology of Freescale Semiconductor Inc., Corporate Headquarters 6501 William Cannon Drive West Austin, Tex. 78735 USA. Both packaging approaches enable close proximity of disparate MMIC technologies by encapsulating both die using silicon backend processing steps, where dielectric and metal layers are photo-lithographically defined to create interconnects that have similar characteristics to the interconnects found in the back end of commercial silicon processes—significantly lower inductance than bondwires. Heterogeneous integration of the III-V and silicon technology would provide similarly low-parasitic interconnects. If more commonplace packaging technologies are used, such as chip-and-wire, passive structures on the III-V die can be used to resonate out the inductance from the bondwires to achieve the desired low parasitic interconnect over a bandwidth of interest.
The inventors have recognized that the III-V switch be designed such that the closed position is close to zero impedance at the frequency of operation. Passive structures in the RF path can optionally be used to tune out the capacitive parasitics associated with the switch device. The baseband filtering section is designed to incorporate the parasitics of the interconnect between III-V and silicon die, such that the parasitics become part of the passband filter response at the input RF frequency. Because the III-V device has inherently higher voltage headroom than silicon technology, both the in-hand and out-of-band linearity achieve a 10-15 dB improvement over the state of the art. The baseband and LO generation circuitry remains in silicon technology, where the relatively large number of devices and calibration procedures to tune the RF Sampler architecture are easily achievable.
The inventors have recognized that using III-V switches as part of an RF Sampler architecture provides a significant improvement in the linearity, making the approach more compatible with the higher performance requirements of military systems. The enhanced RF Sampler architecture provides benefits over traditional III-V based mixer architectures, because the RF filtering function can be performed at baseband to achieve improved filtering response while minimizing insertion loss. Further, while the RF Sampler provides frequency conversion to baseband for a single RF signal, beamforming multiple RF signals as in a phased array antenna requires independent phase control of each RF signal and the summation of all signals into a combined output.
In accordance with one embodiment of the disclosure, a signal sampler is provided having: a column III-V semiconductor having formed therein a plurality of N, where N is an integer, transistor switches coupled to a common input of the sampler fed by the signal, each one of the plurality of N switches taking samples of the signal in response to a train of sampling signals fed to such one of the switches; and a column IV (such as silicon) semiconductor having analog signal processing circuitry and a generator for generating a plurality of N trains of the sampling signals, each one of the plurality of N trains of sampling signals being fed to a corresponding one of the N samplers. Each one of the N trains of sampling signals is generated with a period T and a duty cycle T/N with the sampling signals in one of the plurality of N trains of the sampling signals being delayed with respect to the sampling signals in another one of the plurality of N trains the sampling signals a time T/N.
In one embodiment of the disclosure, the analog signal processing circuitry a controllable time delay for producing the trains of sampling signals in response to a train of pulses, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay and wherein each one of the sampling signals is produced by the time delay with the period T and the duty cycle T/N with the sampling signals in one of the trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains of the sampling signals a time T/N.
In one embodiment of the disclosure, a frequency conversion circuit is provided having a plurality of N signal channels; each being fed an input signal and a train of pluses having a period T and a duty cycle T/N. Each signal channel includes: a sampler coupled the input signal and being responsive to sampling signals; and a controllable time delay for producing the train of sampling signals in response to the train of pulses, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay. Each one of the sampling signals is produced by the time delay in each one of the channels with the period T and the duty cycle T/N with the sampling signals in one of the trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains the sampling signals a time T/N.
With such an arrangement, the time delays between the trains of sampling signals may be independently controlled by the individual controllable time delays.
In one embodiment of the disclosure, a phased array antenna system is provided having: (A) a beam steering computer; (B) a plurality M, where M is an integers, of antenna elements each one being coupled to a corresponding one of a plurality of M antenna ports; (C) a pulse train source, the pulses in the train having a period T, and a duty cycle T/N; (D) a plurality of M frequency conversion/variable time delay circuits. Each one of the M frequency conversion/variable time delay circuits is coupled to a corresponding one of the M antenna ports. Each one of the M frequency conversion/variable time delay circuits comprises: a plurality of N, where N is an integer, signal channels, each one of the N signal channels being coupled to the corresponding one of the one of the M antenna ports. Each one of the signal channels includes: a sampler coupled to said corresponding one of the one of the M antenna ports and responsive to sampling signals fed thereto; a controllable time delay for producing the train of sampling signals to the sampler in such one of the signal channels in response to a train of pulses coupled to the controllable time delay in such one of the signal channels, the controllable time delay imparting a time delay δ to the pulses in the train of pulses coupled to the controllable time delay in such one of the signal channels in accordance with a time delay command signal fed to the controllable time delay by the beam seeing computer. Each one of the sampling signals in the N trains of sampling signals are produced by the controllable time delay in each one of the channels with a period T and a duty cycle T/N with the sampling signals in one of the N trains of the sampling signals being delayed with respect to the sampling signals in another one of the N trains a time T/N.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.